Non-volatile memory devices include memory cells that have at least two stable states. In some non-volatile memory devices, the resistance through a memory cell differs based on the state of the memory cell. The resistance through the memory cell is higher in a first state relative to the resistance through the memory cell in a second state. These memory devices can be reprogrammable or one-time programmable devices.
One type of reprogrammable non-volatile memory known in the art relies on magnetic memory cells. These devices, known as magnetic random access memory (MRAM) devices, include an array of magnetic memory cells. The magnetic memory cells may be of different types. For example, the memory cells can be magnetic tunnel junction (MTJ) memory cells or giant magnetoresistive (GMR) memory cells.
Generally, the magnetic memory cell includes a layer of magnetic film in which the orientation of magnetization is alterable and a layer of magnetic film in which the orientation of magnetization may be fixed or “pinned” in a particular direction. The magnetic film having alterable magnetization is referred to as a sense layer or data storage layer and the magnetic film that is fixed is referred to as a reference layer or pinned layer. In an MTJ memory cell, a barrier layer separates the sense layer and the reference layer.
Conductive traces referred to as word lines and bit lines are routed across the array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Memory cells store a bit of information as an orientation of magnetization in a sense layer at each intersection of a word line and a bit line. The orientation of magnetization in the sense layer aligns along an axis of the sense layer referred to as its easy axis. Magnetic fields are applied to flip the orientation of magnetization in the sense layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer.
In one embodiment, the word lines and bit lines are routed across the array of memory cells to aid in flipping the orientation of magnetization in sense layers. The word lines extend along rows of the memory cells near the sense layers. The bit lines extend along columns of the memory cells near the reference layers. The word lines and bit lines are electrically coupled to a write circuit.
During a write operation, the write circuit selects one word line and one bit line to change the orientation of magnetization in the sense layer of the memory cell situated at the conductors crossing point. The write circuit supplies write currents to the selected word line and bit line to create magnetic fields in the selected memory cell. The magnetic fields combine to switch the orientation of magnetization in the selected memory cell from parallel to anti-parallel or vice-versa.
The resistance through a memory cell differs according to the parallel or anti-parallel orientation of magnetization of the sense layer and the reference layer. The resistance is highest when the orientation is anti-parallel, which can be referred to as the logic “1” state, and lowest when the orientation is parallel, which can be referred to as the logic “0” state. The resistive state of the memory cell can be determined by sensing the resistance through the memory cell.
Word lines and bit lines also aid in sensing the resistance through a memory cell. Word lines, which extend along rows, are electrically coupled to sense layers and bit lines, which extend along columns, are electrically coupled to reference layers. Word lines and bit lines are also electrically coupled to a read circuit to sense the resistance and state of a memory cell.
During a read operation, the read circuit selects one word line and one bit line to sense the resistance of the memory cell situated at the conductors crossing point. The read circuit can supply a voltage across the selected memory cell to generate a current through the memory cell. The current through the memory cell is proportional to the resistance through the memory cell and is used to differentiate a high resistive state from a low resistive state.
Although the memory device is generally reliable, failures can occur that affect the ability of the memory device to store data reliably. The failures include physical failures related to memory cells and sensing failures related to the read circuit.
Physical failures can result from many causes including manufacturing imperfections and aging of the device with use. Failure mechanisms take many forms including shorted memory cells and open memory cells. A shorted memory cell has a resistance value that is much lower than expected. An open memory cell has a resistance value that is much higher than expected. Shorted and open memory cells can affect other memory cells lying in the same row and the same column.
Sensing failures can result from many causes including temperature and voltage changes. The read circuit is calibrated at one set of temperature and voltage values. Where the temperature and/or voltage changes, the read circuit may be out of calibration. In this situation, the read circuit may not accurately sense the state of a memory cell due to calibration problems. To reliably store data in a memory cell, it is important to have information about the condition of the memory cell and whether the read circuit is properly calibrated.